A semiconductor integrated circuit has circuit elements including a transistor generated on a semiconductor material or insulating material or in a semiconductor material and is designed to have an electronic circuit function. Semiconductor integrated circuits are used in a personal computer, cellular phone, and the like, and the demand for sophistication and higher integration thereof has been increasing in recent years.
A semiconductor integrated circuit must undergo operation inspection before shipment because of the need to fulfill a function as an electronic function, and thus, an inspection circuit is generally provided therein in addition to a circuit for normal operation.
Prior-art techniques for operation inspection include ones shown in FIGS. 6 and 7. The prior-art techniques are each a semiconductor integrated circuit having a plurality of flip-flops, each composed of a master latch and a slave latch, and selectors provided corresponding to the flip-flops, respectively. An output terminal of each slave latch is connected to an input terminal of the selector provided corresponding to one of the flip-flops which is different from the flip-flop including the slave latch.
For example, in the technique described in FIG. 6 (hereinafter simply referred to as the “first prior-art technique), the plurality of flip-flops are connected in series to constitute a scan chain by electrically connecting the output terminal of each slave latch and the input terminal of the selector provided corresponding to one of the flip-flops which is different from the flip-flop including the slave latch, and inspection is performed using the scan chain.
In the technique described in FIG. 7 (hereinafter simply referred to as the “second prior-art technique), each flip-flop further has a different test latch, and two-pattern inspection can be performed in scan chain-based inspection. Note that the first and second prior-art techniques are described in detail in Patent Document 1 below.
[Non-patent Document 1]: Bulent I. Dervisouglu et al., “Desig for testability: using scanpath techniques for path-delay test and measurement,” Proceedings of International of International Test Conference, October 1991, pp. 365-374
However, the first prior-art technique is incapable of performing a so-called two-pattern test at the time of inspection. A two-pattern test is an inspection indispensable for a sophisticated, highly integrated circuit which requires checking for signal delays.
On the other hand, although the second prior-art technique is capable of performing a so-called two-pattern test, a test latch needs to be provided in each flip-flop, thus resulting in an increase in the space occupied by the flip-flop.